1. Field of the Invention
The invention relates to a memory device, and more particularly, to a dual port static random access memory (SRAM).
2. Description of the Related Art
As the function of a microprocessor becomes more and more versatile and complex, larger and larger programs or calculations can be operated by the microprocessor. A memory with a large capacity is thus very demanded. How to meet the demand of memory capacity and to fabricate the memories in a lower cost becomes a leading topic in semiconductor manufactures.
According, to the application functions, memories can be categorized into read only memory (ROM) and random access memory (RAM). The read only memory can only perform the read operation, while the random access memory can perform both write and read operations. In terms of data access the read only memory is further categorized into a mask read only memory programmable read only memory (PROM), erasable programmable read only memory (EPROM), and electrically erasable programmable read only memory (EEPROM). Whereas, the random access memory can be further categorized into a static random access memory and a dynamic random access memory (DRAM).
The SRAM is a memory device having the fastest operation speed among the semiconductor memory devices, so that the range of application field is wide. For example, the SRAM can also be applied as a cache memory for computer data access. A typical SRAM cell comprises four transistors and two resistors or six transistors. Compared to other kinds of memory devices, the integration is inferior.
Another dual port SRAM has been developed with a more powerful function of data input/output (I/O) than the above-mentioned single port SRAM. The dual port SRAM typically comprises eight transistors, including six N-type metal-oxide semiconductors (NMOS) NM1 to NM6 and two P-type MOSs (PMOS) PM1 and PM2, as shown in FIG. 1. In addition, two word lines WL1, W12 and four bit lines BL1, BL1, BL2, BL2 are required to perform write and read operations. The layout of six NMOSs and two PMOSs is very asymmetric to affect the performance of the dual port SRAM.